With advances in semiconductor design and fabrication, the circuit density that can be implemented on a given integrated circuit die has steadily increased, leading to higher power consumption and heat generation. Simultaneously, the scaling to finer geometries has exacerbated issues such as sub-threshold leakage current, making the circuits more susceptible to performance degradation due to temperature variations across the die. Thus, it is becoming increasingly important to efficiently remove heat from an integrated circuit die in order to avoid temperature induced failures.
A typical approach to removing heat from an integrated circuit die is to attach a heat sink to the exterior of the semiconductor packaging. A heat sink is commonly understood to increase the dissipation of heat by means of conduction, convection and radiation as a result of the heat sink's high thermal conductivity and relatively large mass and surface area. The package itself is relied upon to provide the thermal pathway from the integrated circuit die to the external heat sink. In a typical embodiment, a die attach material adheres the backside of the integrated circuit die to the package baseplate which may be a leadframe or a plastic or ceramic substrate. The type of material used for the die attach is a function of the package type and performance requirements. Typical materials are epoxy, lead-tin solder and gold alloys.
Unfortunately, such a configuration may result in device reliability failures and other problems. Heat dissipation with this configuration may simply be inadequate for higher power devices. In addition, voids and poor coverage by the die attach layer, as well as inherent local high-power sources in the integrated circuit channel layer, may cause large temperature gradients across the integrated circuit die. These gradients may cause regions of the die to be outside of the optimal operating temperature range, and may also cause mechanical stresses due to non-uniform thermal expansion.
Improved heat dissipation techniques which alleviate or overcome the above-identified problems are disclosed in U.S. patent application Ser. No. 10/879,909, filed Jun. 29, 2004 and entitled “Heat Sink Formed of Multiple Metal Layers on Backside of Integrated Circuit Die,” which is incorporated by reference herein. In one illustrative arrangement, an integrated circuit die includes a substrate having a front surface and a back surface, with the substrate front surface having electrical circuits formed thereon, and the substrate back surface having a plurality of metal layers formed thereon. The plurality of metal layers comprises at least one layer having a thickness of greater than about ten micrometers. The outermost metal layer may be mechanically and thermally bonded to a package using a die attach layer comprising a thermally conductive reflowable material. The metal layers are configured such that delamination, fracturing and metal diffusion into the substrate are avoided, while heat dissipation is increased.
Despite the considerable advances provided by the techniques disclosed in the above-cited U.S. patent application Ser. No. 10/879,909, a need remains for further improvements, particularly in terms of localized heat removal from high-power sources or “hot spots” on an integrated circuit die.
A number of prior art approaches address this localized heat removal issue through the use of heat transfer structures which are arranged within the integrated circuit die itself. These include U.S. Pat. No. 5,621,616 to Owens et al., entitled “High Density CMOS Integrated Circuit with Heat Transfer Structure for Improved Cooling,” U.S. Pat. No. 6,046,503 to Weigand et al., entitled “Metalization System Having an Enhanced Thermal Conductivity,” and U.S. Pat. No. 6,100,199 to Joshi et al., entitled “Embedded Thermal Conductors for Semiconductor Chips,” all of which are incorporated by reference herein.
However, these conventional approaches fail to provide an adequate solution to the problem of localized heat removal from high-power sources or other hot spots on an integrated circuit die. A need therefore exists for improved heat dissipation techniques for use in integrated circuits.